The present invention relates to testing of complex combinatorial and sequential logic circuits embodied in large scale integration (LSI) and very large scale integration (VLSI) circuit devices and more particularly, to the reduction of power dissipation and heating of circuit elements during testing.
A fault occurring anywhere in a LSI or VLSI circuit device can have its effect propagated through a number of feedback loops including storage or memory elements in the sequential logic before reaching a testable output of the device. Level sensitive scan design (LSSD) rules were devised to eliminate the complications in testing caused by this propagation through feedback loops. As described by E. B. Eichelberger and T. W. Williams in an article entitled xe2x80x9cA Logic Design Structure for LSI Testabilityxe2x80x9d on pages 462-468 of the Proceedings of the 14th Design Automation Conf, LSSD rules impose a clocked structure on logic circuit memory elements such as latches and registers, and require these memory elements be tied together to form a shift register scan path so that they are accessible for use as test input and output points. Therefore, test input signals can be introduced or test results observed wherever one of the memory elements occurs in the logic circuit. Being able to enter the logic circuit at any memory element for introducing test signals or observing test results, allows the combinational and sequential logic to be treated as much simpler combinational logic for testing purposes thus considerably simplifying test generation and analysis. Patents describing LSSD techniques include U.S. Pat. Nos. 3,783,254; 3,784,907; 3,961,252, 4,513,418 and 5,983,380. The subject matter of these patents and the above described Eichelberger and Williams article are hereby included by reference.
Self-testing has been employed in connection with LSSD to reduce the volume of text patterns and time it takes to generate the test patterns and to perform the testing. Self-testing involves the use of pseudo-random pattern generators and response compression structures that are built into logic circuit devices. Using such pattern generators and compression structures eliminates the computer time needed to generate the tests and placing these testing elements on the device containing the logic allows the application of vast numbers of test patterns to the circuits in a high ratio and in a reasonable period of time.
In the aforementioned U.S. Pat. No. 5,983,380, the shift register latches (SRLs) in the LSSD scan paths perform both input data launching and output data capturing. The test patterns come from the scan path that is configured into a linear feedback shift register (LFSR). The test data is then outputted into a multiple input shift register (MISR) for data compression. Alternate scan path shift cycles are applied to the SRLs exercising the combinational logic with the contents of the SRLs and capturing the results of the response back into the SRLs where they can be used as test inputs for the next cycle. At the end of a calculated number of cycles, the contents of the scan path are read out as the signature to be compared with the desired value. Such self-testing is referred to as Logic Built-In Self-Test (LBIST).
Two types of LBIST tests are applied during self test. One type is the LBIST test and another is the weighted LBIST test. As shown in FIG. 1, the LBIST and weighted LBIST tests are performed sequentially with the weighted LBIST test usually following the LBIST test. One problem with this test strategy is that the AC power consumption during LBIST can be very high and as more and more devices are included in the design, the heating of circuit elements will become a severe problem. There are two factors of power consumption during test. One is during the scan session where logic switching activities occurs while loading the scan chain with random patterns. The other is during the test cycle where system clocks are applied. In LBIST, the typical test patterns used make the chip function at 50% switching activity per system clock, which can cause a large power supply droop during high speed testing since the power consumption is proportional to the summation of switching activities of individual devices.
In accordance with the present invention, the flat LBIST and weighted LBIST test patterns are simultaneously provided different portions of the tested circuit element. This new test methodology and design change achieves the same test coverage and test time as the traditional test strategy with dramatic power reduction during test. It can be applied at wafer, chip, multi chip module (MCM), and system levels of test. Most importantly, it does not need new tools for support. Current test software will work as it does with the traditional test strategy. Scheduling the LBIST and weighted LBIST tests in the same test session reduces the power consumption (watts) because weighted LBIST pattern testing consumes much less power than flat pattern LBIST testing. In the same test session, if some parts of the logic is tested using weighted LBIST while the others were tested using LBIST, the power consumed by the circuit element at any given time is reduced.
Therefore, it is an object of the present invention to provide improved LSSD testing methods and apparatus.
It is another object of the present invention to provide for more efficient testing of logic circuits.
It is a further object of the invention to provide improved testing procedures.